1. Field of the Invention
This invention deals with the simultaneous control and management of plural bubble memory devices and the blemished data positions contained within them. A blemished data position is a data position in a memory device which does not allow proper retrieval of data stored in it. Data retrieved from blemished data positions may always be a "0", a "1", or may be a random value, depending on the nature of the defect. The external data source or utilization device using the bubble memory devices is totally unaware of the existence and effect of the blemished data positions within the bubble memory devices, with the exception of the reduction in total storage data capacity caused by the blemished data positions.
2. Description of the Prior Art
In the production of solid state memory chips for use in computer memories the number of defective parts manufactured may far outnumber the production of perfect parts. Of course, defective parts are typically discarded. If a method could be devised for using defective parts the per unit cost of such devices could be substantially reduced. The prior art has disclosed a number of methods for the utilization or correction of partially defective solid state memory devices such as magnetic bubble memories. Some methods disclosed take advantage of certain modes of defects found in certain types of solid state memory devices. Other inventions disclosed general methods to correct errors in arbitrary types of memory systems. A third class of inventions disclose methods for the internal correction of errors in particular types of solid state memory devices. Such methods introduce additional complexities into the internal organization of the devices in order to mask the existence of the production defects.
An example of the first approach can be found in U.S. Pat. No. 4,045,779 to R. Markle whereby a method is disclosed for correcting errors in random access memory chips. The method is meant to correct errors of the type where no more than one of the bits in a memory word is permanently "stuck" at either a 1 or a 0. The method allows for the correction of an arbitrary number of such errors within the memory system so long as the errors are in the specified class. The method provides for separate storage of the addresses of memory words containing the errors and also for the storage of a flag bit for each of the memory words containing an error. When data is to be stored in a memory word known to contain a defective bit, the fact that the address matches an address in the separate error address memory storage is recognized. After the data is stored in the memory system, it is retrieved and compared to what was to have been stored there. If a difference is detected, the flag bit is set and the data to be stored in that word is complemented and rewritten. In this manner, due to the characteristics of the defect which are assumed, upon retrieval of the data from the memory word the flag bit will indicate that the data should be complemented. In this way, the error is corrected without action by the computer system external to the controlling circuitry for the memory system. Unlike the invention disclosed herein, this scheme requires additional memory cells above to be read or written. These cells are used as the flags to determine whether or not to complement the data fetched from memory addresses known be blemished. In addition, as previously mentioned, this method can be used only where the memory words contain a single bit error at most. This particular class of error is not the general type found with bubble memory systems containing blemishes within individual devices. Therefore, this scheme is inappropriate to bubble memory devices. In addition, the invention disclosed herein uses no scheme of complementing of data being stored in memory words containing blemishes.
Another class of method found in the prior art is typified by U.S. Pat. No. 4,032,765 to J. Epstein, et al. This prior art reveals a general method for the correction of data stored in memory words containing known blemishes. The invention disclosed in this patent provides for the storage of addresses containing known memory defects. In addition, for each of these memory addresses, sufficient auxiliary memory storage is provided to contain the data which was to have been stored in the memory word containing the blemish. Means are revealed to detect the attempted storage into memory words containing blemishes and for the routing of that data into the auxiliary memory storage. Retrieval of data from memory words containing known defects is routed to the auxiliary memory storage where it is fetched and patched into the memory bus as though the data were actually being provided from the main memory storage. Unlike the herein disclosed invention, this prior art requires additional storage able to be written into which will store the data meant to go to the memory addresses containing known errors. Such schemes requiring auxiliary read/write memory are not the most desirable means in order to correct memory systems since the auxiliary read/write memory must itself be defect free or have its own scheme for correcting its known defects. The invention disclosed herein requires no auxiliary read/write memory. All data is stored in the bubble memory devices, thereby eliminating the need for additional auxiliary read/write memory.
Magnetic bubble memory devices are a relatively new means of providing memory storage for computer systems. The methods of integrating such devices into existing computer technology is an area of technological endeavor of great current interest in the field. The prior art has disclosed several schemes which attempt to compensate for the production flaws often found within these devices. A magnetic bubble device can be roughly analogized as a shift register storage containing many bits of information. A blemish in the device may cause a series of regularly spaced data positions within the device to be inoperative. As data is shifted out of the device in a serial manner, the blemishes cause these positions to contain invalid data. These positions must therefore not be used for data storage and the contents of these positions must be ignored when the device is used for data retrieval.
The typical internal architecture of a magnetic bubble device consists of a number of minor loops containing the actual data. Each loop consists of a number of magnetic bubbles able to store one bit of data. The minor loops are like circular shift registers which can be stepped in unison. In close proximity to each minor loop is a transfer station which allows data to be transferred between each loop and a major loop. The major loop is the means for distributing data received by the device to the various minor loops used for the actual data storage.
U.S. Pat. No. 4,001,673 to G. Barrett, et al. suggest a method to "repair" a single bubble memory device containing blemishes. After detection of the defective data positions, the invention discloses a means for shorting out minor loops containing a blemish. The shorting out of the minor loops is done within the magnetic bubble device itself. A new construct within the device, called "repair stations", is used to effectively remove blemished minor loops from the device. As a result, the effective storage of each such "repaired" bubble memory device is variable, depending upon the number of blemished minor loops which are removed. Such resulting chips are difficult to incorporate into a memory system since they contain a variable number of effective data positions within them. Furthermore, the method requires additional approaches such as repair stations within each bubble memory device, complicating the internal organization of each such device. The invention disclosed herein is a means for blemish correction of plural bubble memories. It requires no additional correction or repair mechanism within the individual bubble memory devices.
U.S. Pat. No. 3,792,450 to J. Bogar et al. discloses an invention for the avoidance of data positions containing blemishes within a single bubble memory device. The control means includes within the device a control loop containing information as to the existence of the blemished minor loops. External circuitry uses the control loop information to inhibit data transfer to or from blemished data loops. This invention once again requires additional complexity within the bubble memory device. In this case, a control loop is required for the storage of the positions of the blemished minor loops. In addition, the effective storage of each bubble memory device depends upon the number of blemished minor loops.
FIG. 1 diagrams the functional operation of a method for controlling a bubble memory device like that proposed in the Bogar patent. A bubble memory device 101 contains the data positions used for storage 103 and the control loop 102 storing the information as to the locations of the blemished data positions. The squares indicate valid data positions within the bubble memory device 101, these positions able to be used for storage and retrieval of information. The X's indicate data positions within the bubble memory device which are blemished. The control circuitry 104 external to the bubble memory device 101, uses the information contained in the control loop 102 to manage the transfer of data between the external parallel bus 105 and the bubble memory device 101. The numbers within the lower right hand corner of the squares indicate the order in which the control circuitry 104 will store the data as received from the parallel bus. As indicated, the control circuitry 104 will properly skip the blemished data positions in the storage of data. This scheme could be characterized as one in which data received in parallel is disassembled into a serial data stream, said stream being interrupted by the control loop memory so as to cause the blemished data positions to not be used for data storage. Although this method is quite suitable for the control and management of a single bubble memory device, the scheme is inappropriate for use in a memory system containing many bubble memory devices inasmuch as the control circuitry disassembles a parallel input stream into a single serial data stream to a single bubble memory device. Required in a bubble memory system containing multiple bubble memory devices is a control means whereby parallel data can be received from the external circuitry and an independent parallel interface to the multiple bubble memory devices is supported. An object of the present invention is to provide such a system.